Shodhganga : a reservoir of Indian theses @ INFLIBNET
The Shodhganga@INFLIBNET Centre provides a platform for research students to deposit their Ph.D. theses and make it available to the entire scholarly community in open access.
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/321727
| Title: | Design and Modelling of All Digital Phase Locked Loop Using VLSI |
| Researcher: | Anupama P. Patil |
| Guide(s): | P.H. Tandel |
| Keywords: | Computer Science Computer Science Artificial Intelligence Engineering and Technology |
| University: | Pacific University |
| Completed Date: | 2019 |
| Abstract: | newline |
| Pagination: | |
| URI: | http://hdl.handle.net/10603/321727 |
| Appears in Departments: | computer science |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 01_cover page - anupama patil.pdf | Attached File | 67.99 kB | Adobe PDF | View/Open |
| 02_certificate by supervisor.pdf - anupama patil.pdf | 67.24 kB | Adobe PDF | View/Open | |
| 03_acknowledgment and abstract - anupama patil.pdf | 58.53 kB | Adobe PDF | View/Open | |
| 80_recommendation.pdf | 53.71 kB | Adobe PDF | View/Open | |
| addpll thesis chapter 1 final - anupama patil.pdf | 132.05 kB | Adobe PDF | View/Open | |
| addpll thesis chapter 2 final - anupama patil.pdf | 186.05 kB | Adobe PDF | View/Open | |
| addpll thesis chapter 3 final - anupama patil.pdf | 1.45 MB | Adobe PDF | View/Open | |
| addpll thesis chapter 4 final - anupama patil.pdf | 532.45 kB | Adobe PDF | View/Open | |
| chapter 5finaladpll - anupama patil.pdf | 1.31 MB | Adobe PDF | View/Open |
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