Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/321461
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dc.date.accessioned2021-04-21T05:26:02Z-
dc.date.available2021-04-21T05:26:02Z-
dc.identifier.urihttp://hdl.handle.net/10603/321461-
dc.description.abstractDigital image processing is an ever elaborating and active area with applications reaching out into our everyday life such as medicine, space exploration, surveillance, authentication, automated industry review and many more areas. Applications such as these require different processes like image enhancement and object detection. Median filtering is a powerful instrument used in image processing. The traditional median filtering algorithm, without any modifications gives good results. There are many variations to the classical algorithm, aimed at reducing computational cost or to achieve additional properties. Median filters are used mainly to remove salt-and pepper noise. The filter logic is implemented on a novel reconfigurable fabric. In this paper look into a Efficient architecture for non-linear modified Adaptive median filter implementation is presented. Then Adaptive Median Filter solves the dual purpose of removing the impulse noise from the image and reducing distortion in the image and the classical adaptive median filter has some deficiencies: the filtered images remain the positive impulse noise in the black background and the negative impulse noise in the white background. To solve the above questions, a modified scheme is proposed. The practical results show the effectiveness of our improvements allowing real-time processing and a minimum use of resources. newline
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dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleA Novel High Speed Parallel Scheme For Data Sorting Algorith In Median Filter Based On FPGA
dc.title.alternative
dc.creator.researcherBALARANI, R
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
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dc.publisher.placeChennai
dc.publisher.universityBharath University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered
dc.date.completed2012
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

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80_recommendation.pdfAttached File386.75 kBAdobe PDFView/Open
certificate.pdf174.15 kBAdobe PDFView/Open
chapter 1.pdf339.57 kBAdobe PDFView/Open
chapter 2.pdf348.72 kBAdobe PDFView/Open
chapter 3.pdf407.67 kBAdobe PDFView/Open
chapter 4.pdf689.32 kBAdobe PDFView/Open
chapter 5.pdf991.91 kBAdobe PDFView/Open
chapter 6.pdf211.68 kBAdobe PDFView/Open
preliminary pages.pdf637.96 kBAdobe PDFView/Open
references.pdf566.41 kBAdobe PDFView/Open
title.pdf182.69 kBAdobe PDFView/Open


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