Energy Efficient Parallel Prefix Adders Employing HighValency Jackson Recursion and Tree Sparseness

Abstract

The core of every microprocessor, digital signal processor (DSP) and data processing application-specific integrated circuit (ASIC) is its data path. Most of the performance parameters such as the die area, power dissipation and operating speed are decided by the data path of the processor. Arithmetic Logic Unit (ALU) is the most critical block in the data path of a processor. Switching at the highest rate of frequencies, ALU tend to be the possible locations for thermal hot spots. The presence of multiple ALUs in the pipelined architectures further aggravates the problem. Furthermore, the clock frequency of a processor is decided by the speed of ALU, since it decides the critical path of an instruction execution. Addition is the most commonly used and speed limiting operation in the ALU and the role of an adder is not limited only to addition process. It forms the building block of many other basic arithmetic operations such as subtraction, increment/decrement and multiplication, to name a few. Thus, for bettering the performance of a processor, efficient realization of adder is very crucial. There exist several methods to formulate addition operation. All these methods incur various performance metrics. Among them, the most commonly used solution for integer addition is the parallel prefix addition