Design and Development of Fixed Width Radix 8 Booth Multipliers for High Accuracy and Low Power Operation

Abstract

Multiplier is one of the most essential and fundamental components in many multimedia and Digital Signal Processing (DSP) Systems. They play very important role since they can greatly influence the performance and the power dissipation of the system. Thus, for better performance of such systems, efficient realization of multiplier is verycrucial. Many DSP applications employ fixed-point arithmetic where n bit signals aremultiplied by n bit coefficients. To avoid infinite growth in the word size, 2n bit products obtained must be quantized to n bits. Also many multimedia systems maintain a fixed format and tolerate some loss in the accuracy where precision may be compromised for achieving improvisation in performance parameters, viz. speed, area and power dissipation. In such applications, fixed-width multipliers revests to be one of the solutions towards enhancing the speed, reducing the area and power dissipation. Fixed-width multiplier is a n x n multiplier with n bits output. In fixed-width multipliers, half of the adder cells that add n least significant bits are removed and replaced by a suitable compensation bias to tradeoff accuracy and hardware cost. Various compensation techniques have been proposed in the literature for fixed-width radix-4 Booth multipliers to achieve high accuracy and low power in comparison with conventional multipliers. All these methods incur various performance metric and there exist a tradeoff between accuracy and hardware cost