Investigations in Techniques to Improve the Reliability of Memristor Memories

Abstract

Memristor-based memory technology also referred to as resistive random access newlinememory (RRAM), is one of the emerging memory technologies potentially to replace newlineconventional semiconductor memories such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and flash. The advantages of Memristor memories include non-volatility, high density, low power consumption, fast operating speed, and ability to function as multi-level cell (MLC). In spite of having numerous advantages, they are highly prone to process variations. The non-deterministic nature of memristor and its unreliable behavior are the two main concerns hampering its growth and industrial manufacturing. The endurance and reliability of memristor memories are affected not only by the process variations but also due to the electrical stress created by interfacing peripheral circuits. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, and fabrication techniques. However, research on manufacturing, test for yield, reliability and quality improvement is still in its infancy stage. The objective of this research work is to design a Built-In Self- Test (BIST) and Built-In Self-Configurable (BISC) circuits to improve the endurance and reliability of the memristor-based memories. The proposed techniques under various memristor faults are found to enhancing the reliability of memristors efficiently newline