Sbox Primitive in Symmetric Lightweight Block Ciphers Design Solutions for Resource Constrained Applications

Abstract

Tailored application specific implementations of lightweight cryptographic primitives newlineprovide promising security solutions with limited resource utilization and lower newlinepower consumption. Substitution box (S-box) is the non-linear operation involved in newlinesymmetric lightweight block ciphers and it significantly influences the hardware performance and security characteristics of overall cipher to a greater extent. newlineThis research investigation concentrates on the lightweight hardware design of the newlinenibble S-box in lightweight block ciphers. The work devises non Look-Up Table combinational structures for S-box in two distinct strategies, namely, 1) novel lightweight, compact and optimally secure nibble S-box in finite fields and 2) Reed Muller (RM) structure for S-box specification in lightweight block ciphers and its optimization using a novel mechanism, called Rule Based-Common Sub-structure Sharing optimization (RB - CSSO). The increasing pervasiveness of smart devices makes them prone to realistic implementation attacks. A side channel power analysis robust and energy efficient charge recovery based circuit style has been proposed to counteract the implementation assaults in the circuit level abstraction of design solution. Results are validated by incorporation of a novel S-box structure in basic loop architecture of ISO standardized PRESENT lightweight block cipher. 5% lower gate equivalent area has been consumed by proposed S-box in PRESENT lightweight cipher loop architecture than the Look-Up Table (LUT) based S-box of same architecture. Linear and differential cryptanalysis bounds of the novel S-box in n-bit block cipher are estimated to prove its algorithmic cryptanalytic resistance. Pre-layout and postlayout simulations of optimized RM structure have been studied in terms of power-area product, power-delay product and area-delay product under a range of PVT corners and different operating conditions. The proposed optimization leads to 12% and 26% average percentage of reduction in AND gates and XOR gates, respec