Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/318291
Title: Design Analysis and Implementation of Chaotic System for Secure Communication
Researcher: Gugapriya, G
Guide(s): Lakshmi, B
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: VIT University
Completed Date: 2020
Abstract: The research work designs two chaotic systems. The first one is the conservative newlinechaotic systems with cyclic symmetry whose novelty is that its volume is conservative in nature and such systems are less investigated in the literature. The forward and backward continuation of the chaotic system are presented and proved that the conservative chaotic systems possess special intricate behaviors such as multistability and coexisting attractors. The second one is the chaotic systems with multiscroll hyperbolic functions which are used for chaotic encryption. Dynamic properties of these two systems are derived and analyzed. To check for the region of chaos, bifurcation analysis is done. To show the existence of chaotic oscillations, Lyapunovspectrum is derived. The integer order treatment of the multiscroll hyperbolic chaoticsystem confirms the existence of bistability, multiscroll and symmetric properties. To show the hardware reliability, these systems are implemented in Field Programmable Gate Array (FPGA). Using Grunwald - Letnikov (G-L) method, the multiscroll hyperbolic chaotic system is analyzed with its fractional order form. By using the fractional order analysis, the system can be analyzed more accurately. The numerical simulations for various order q is studied and confirmed that the above said properties still remain in the system. Thus the complexity of the system is increased. By varying only the fractional order q multiscroll property is achieved. This is a novel method to bring out multiscroll behavior. In order to show that the systems are suitable for secure communication applications, adaptive synchronization using sliding mode control scheme is presented. The discrete integrators required for solving the initial value problem are implemented using the Euler s method. The hardware-software co-simulation is used to generate phase portraits of the FPGA implemented systems. In order to save the hardware resources, the multipliers used are Single Constant Multipliers (SCM).
Pagination: i-xiii, 1-119
URI: http://hdl.handle.net/10603/318291
Appears in Departments:School of Electronics Engineering-VIT-Chennai

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01_tiltle page.pdfAttached File130.73 kBAdobe PDFView/Open
02_declaration & certifigate.pdf86.12 kBAdobe PDFView/Open
03_abstract.pdf110.13 kBAdobe PDFView/Open
04_acknowledgement.pdf66.95 kBAdobe PDFView/Open
05_table of contents.pdf226.29 kBAdobe PDFView/Open
06_list of figures.pdf411.99 kBAdobe PDFView/Open
07_list of tables.pdf91 kBAdobe PDFView/Open
08_list of symbols and abbreviations.pdf203.32 kBAdobe PDFView/Open
09_chapter_01.pdf2.07 MBAdobe PDFView/Open
10_chapter_02.pdf1.21 MBAdobe PDFView/Open
11_chapter_03.pdf2.39 MBAdobe PDFView/Open
12_chapter_04.pdf5.2 MBAdobe PDFView/Open
13_chapter_05.pdf4.91 MBAdobe PDFView/Open
14_chapter_06.pdf2.83 MBAdobe PDFView/Open
15_chapter_07.pdf1.8 MBAdobe PDFView/Open
16_chapter_08.pdf90.21 kBAdobe PDFView/Open
17_references.pdf955.01 kBAdobe PDFView/Open
18_list of publications.pdf84.51 kBAdobe PDFView/Open
19_appendix.pdf79.88 kBAdobe PDFView/Open
80_recommendation.pdf221.26 kBAdobe PDFView/Open
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