Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/317951
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dc.coverage.spatialEngineering
dc.date.accessioned2021-03-10T12:56:19Z-
dc.date.available2021-03-10T12:56:19Z-
dc.identifier.urihttp://hdl.handle.net/10603/317951-
dc.description.abstractfile attached
dc.format.extent110 p.
dc.languageEnglish
dc.relationno. of references 50
dc.rightsuniversity
dc.titleA low power delay product hybrid CMOS full adder design for chain and tree structures and its characterization
dc.title.alternative-
dc.creator.researcherMewada, Manan Rajanikant
dc.subject.keywordArithmetic and Logic Unit
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordInstruments and Instrumentation
dc.subject.keywordPortable electronic devices
dc.subject.keywordProcessors
dc.description.notebibliography p.76-82
dc.contributor.guideZaveri, Mazad S
dc.publisher.placeAhmedabad
dc.publisher.universityAhmedabad University
dc.publisher.institutionSchool of Engineering and Applied Science
dc.date.registered
dc.date.completed2019
dc.date.awarded
dc.format.dimensions-
dc.format.accompanyingmaterialNone
dc.type.degreePh.D.
dc.source.inflibnetINFLIBNET
Appears in Departments:School of Engineering and Applied Science

Files in This Item:
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01_title.pdfAttached File47.73 kBAdobe PDFView/Open
02_copyright.pdf85.65 kBAdobe PDFView/Open
03_declaration.pdf47.87 kBAdobe PDFView/Open
04_certificate.pdf47.85 kBAdobe PDFView/Open
05_abstract.pdf79.76 kBAdobe PDFView/Open
06_acknowledgements.pdf56.48 kBAdobe PDFView/Open
07_content.pdf129.71 kBAdobe PDFView/Open
08_chapter 1.pdf216.25 kBAdobe PDFView/Open
09_chapter 2.pdf3.76 MBAdobe PDFView/Open
10_chapter 3.pdf4.8 MBAdobe PDFView/Open
11_chapter 4.pdf6.25 MBAdobe PDFView/Open
12_chapter 5.pdf3.48 MBAdobe PDFView/Open
13_publications.pdf69.5 kBAdobe PDFView/Open
14_bibliography.pdf95.94 kBAdobe PDFView/Open
15_appendix.pdf36.06 MBAdobe PDFView/Open
80_recommendation.pdf89.43 kBAdobe PDFView/Open


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