1. Shodhganga@INFLIBNET
  2. Ahmedabad University
  3. School of Engineering and Applied Science
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/317951
Title: A low power delay product hybrid CMOS full adder design for chain and tree structures and its characterization
Researcher: Mewada, Manan Rajanikant
Guide(s): Zaveri, Mazad S
Keywords: Arithmetic and Logic Unit
Engineering
Engineering and Technology
Instruments and Instrumentation
Portable electronic devices
Processors
University: Ahmedabad University
Completed Date: 2019
Abstract: file attached
Pagination: 110 p.
URI: http://hdl.handle.net/10603/317951
Appears in Departments:School of Engineering and Applied Science

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01_title.pdfAttached File47.73 kBAdobe PDFView/Open
02_copyright.pdf85.65 kBAdobe PDFView/Open
03_declaration.pdf47.87 kBAdobe PDFView/Open
04_certificate.pdf47.85 kBAdobe PDFView/Open
05_abstract.pdf79.76 kBAdobe PDFView/Open
06_acknowledgements.pdf56.48 kBAdobe PDFView/Open
07_content.pdf129.71 kBAdobe PDFView/Open
08_chapter 1.pdf216.25 kBAdobe PDFView/Open
09_chapter 2.pdf3.76 MBAdobe PDFView/Open
10_chapter 3.pdf4.8 MBAdobe PDFView/Open
11_chapter 4.pdf6.25 MBAdobe PDFView/Open
12_chapter 5.pdf3.48 MBAdobe PDFView/Open
13_publications.pdf69.5 kBAdobe PDFView/Open
14_bibliography.pdf95.94 kBAdobe PDFView/Open
15_appendix.pdf36.06 MBAdobe PDFView/Open
80_recommendation.pdf89.43 kBAdobe PDFView/Open
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