Implementation of wide bandwidth sigma delta analog to digital converter using 180nm CMOS technology

Abstract

The advent of System on Chip (SoC) era has created new avenues in the direction of realizing a complete receiver system on a single chip. Further, the drastic growth of communication industry has led to a newlineplethora of wireless handheld applications that require wide-bandwidth and very low power consumption. The most important block in a receiver system is the analog to digital converter which decides the partitioning point between the analog and digital part of the receiver. With the thrust on reducing the analog components and increasing the digital processing newlinepart, today s analog and mixed signal design engineers face a typical problem of balancing speed, power and area and performing an appropriate tradeoff between them, based on requirement. In this thesis the feasibility of using sigma-delta analog to digital converters for wide-bandwidth applications is studied. Sigma-delta converters have established themselves as the preferred choice of newlineimplementation for low frequency audio applications providing resolutions of upto 24 bits. The thesis presents various techniques to extend the use of sigma-delta converters at high frequencies targeted at GSM band(200 KHz bandwidth) and CDMA band(5 MHz bandwidth) providing resolutions of 14 bits and 8 bits respectively. This has been made possible by a paradigm shift from the conventional discrete time modulators to continuous time modulators that can operate at high newlineoversampling frequencies.