Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/314527
Title: | Hybrid Central Processing Unit Field Programmable Gate Array Design for High Performance Computing |
Researcher: | Jeanshilpa V. |
Guide(s): | Jawahar P.K. |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | B S Abdur Rahman University |
Completed Date: | 2020 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/314527 |
Appears in Departments: | Department of Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
80_recommendation.pdf | Attached File | 222.13 kB | Adobe PDF | View/Open |
abstract.pdf | 785.74 kB | Adobe PDF | View/Open | |
chapter1.pdf | 854.24 kB | Adobe PDF | View/Open | |
chapter2.pdf | 951.87 kB | Adobe PDF | View/Open | |
chapter3.pdf | 1.3 MB | Adobe PDF | View/Open | |
chapter4.pdf | 1.4 MB | Adobe PDF | View/Open | |
chapter5.pdf | 1.6 MB | Adobe PDF | View/Open | |
chapter6.pdf | 1.27 MB | Adobe PDF | View/Open | |
chapter7.pdf | 734.51 kB | Adobe PDF | View/Open | |
references.pdf | 816.95 kB | Adobe PDF | View/Open | |
table of content.pdf | 819.07 kB | Adobe PDF | View/Open |
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