Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/314527
Title: Hybrid Central Processing Unit Field Programmable Gate Array Design for High Performance Computing
Researcher: Jeanshilpa V.
Guide(s): Jawahar P.K.
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: B S Abdur Rahman University
Completed Date: 2020
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/314527
Appears in Departments:Department of Electronics and Communication Engineering

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abstract.pdf785.74 kBAdobe PDFView/Open
chapter1.pdf854.24 kBAdobe PDFView/Open
chapter2.pdf951.87 kBAdobe PDFView/Open
chapter3.pdf1.3 MBAdobe PDFView/Open
chapter4.pdf1.4 MBAdobe PDFView/Open
chapter5.pdf1.6 MBAdobe PDFView/Open
chapter6.pdf1.27 MBAdobe PDFView/Open
chapter7.pdf734.51 kBAdobe PDFView/Open
references.pdf816.95 kBAdobe PDFView/Open
table of content.pdf819.07 kBAdobe PDFView/Open
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