Intelligent Reconfigurable Audio Processor Design with Reconfigurable on Chip Communication Wrapper Module

Abstract

With the increase in the heterogeneous components in a Multi newlineProcessor System on chip, intercommunication between the different IP newlinecores or blocks in a SoC turns out to be a problem. The Proposed newlinearchitecture helps to use the resources efficiently through runtime newlinereconfiguration of the communication channel as per the communication newlinerequirements. This reconfigurable NoC architecture could be the solution newlinefor growing communication demands, Quality of service, decreased silicon newlinerate and network scalability. newlineThis research work focuses on the design of a Reconfigurable newlineCommunication Wrapper that allows easy communication between the newlineheterogeneous IP cores. The efficiency of the proposed wrapper based on newlinechip communication link is improved through optimization using Genetic newlineAlgorithm. A Reconfigurable Audio Processor has been implemented as an newlineapplication to prove the performance of the proposed reconfigurable newlinecommunication wrapper. Reconfigurable audio processor is one which has a newlinecapability of reconfiguring the communication blocks of the on-chip newlinecommunication link based on the speaker setup on which audio has to be newlineplayed and the quality of audio file. The proposed solutions were simulated newlineand tested. The simulation results of the proposed system are presented. The newlineperformance of the processor is evaluated in terms of space complexity of newlinethe system and power consumption. The accuracy of the audio conversion is newlineaccessed by means of the peak signal to noise ratio. newline newline newline