Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/314176
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dc.coverage.spatial
dc.date.accessioned2021-02-03T11:11:10Z-
dc.date.available2021-02-03T11:11:10Z-
dc.identifier.urihttp://hdl.handle.net/10603/314176-
dc.description.abstractAbstract available
dc.format.extent149p
dc.languageEnglish
dc.relation121-149
dc.rightsuniversity
dc.titleA Study on the integration issues of high k gate dielectrics on hetero epilayers for advanced nano scale MOS devices
dc.title.alternative
dc.creator.researcherDas, Anindita
dc.subject.keywordPhysical Sciences
dc.subject.keywordMultidisciplinary
dc.subject.keywordNanoscience and Nanotechnology
dc.description.note
dc.contributor.guideChattopadhyay, Sanatan
dc.publisher.placeKolkata
dc.publisher.universityUniversity of Calcutta
dc.publisher.institutionDepartment of Nanoscience and Nanotechnology
dc.date.registered
dc.date.completed2018
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Nanoscience and Nanotechnology

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01_title page.pdfAttached File79.58 kBAdobe PDFView/Open
02_abstract.pdf90.29 kBAdobe PDFView/Open
03_acknowledgement.pdf79.53 kBAdobe PDFView/Open
04_content.pdf303.32 kBAdobe PDFView/Open
05_list of publication.pdf80.2 kBAdobe PDFView/Open
06_chapter 1.pdf299.28 kBAdobe PDFView/Open
07_chapter 2.pdf579.44 kBAdobe PDFView/Open
08_chapter 3.pdf2.12 MBAdobe PDFView/Open
09_chapter 4.pdf2.98 MBAdobe PDFView/Open
10_chapter 5.pdf2.16 MBAdobe PDFView/Open
11_chapter 6.pdf581.43 kBAdobe PDFView/Open
12_chapter 7.pdf139.79 kBAdobe PDFView/Open
13_references.pdf296.02 kBAdobe PDFView/Open
80_recommendation.pdf79.58 kBAdobe PDFView/Open


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