Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/314176
Title: A Study on the integration issues of high k gate dielectrics on hetero epilayers for advanced nano scale MOS devices
Researcher: Das, Anindita
Guide(s): Chattopadhyay, Sanatan
Keywords: Physical Sciences
Multidisciplinary
Nanoscience and Nanotechnology
University: University of Calcutta
Completed Date: 2018
Abstract: Abstract available
Pagination: 149p
URI: http://hdl.handle.net/10603/314176
Appears in Departments:Department of Nanoscience and Nanotechnology

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01_title page.pdfAttached File79.58 kBAdobe PDFView/Open
02_abstract.pdf90.29 kBAdobe PDFView/Open
03_acknowledgement.pdf79.53 kBAdobe PDFView/Open
04_content.pdf303.32 kBAdobe PDFView/Open
05_list of publication.pdf80.2 kBAdobe PDFView/Open
06_chapter 1.pdf299.28 kBAdobe PDFView/Open
07_chapter 2.pdf579.44 kBAdobe PDFView/Open
08_chapter 3.pdf2.12 MBAdobe PDFView/Open
09_chapter 4.pdf2.98 MBAdobe PDFView/Open
10_chapter 5.pdf2.16 MBAdobe PDFView/Open
11_chapter 6.pdf581.43 kBAdobe PDFView/Open
12_chapter 7.pdf139.79 kBAdobe PDFView/Open
13_references.pdf296.02 kBAdobe PDFView/Open
80_recommendation.pdf79.58 kBAdobe PDFView/Open
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