Shodhganga : a reservoir of Indian theses @ INFLIBNET
The Shodhganga@INFLIBNET Centre provides a platform for research students to deposit their Ph.D. theses and make it available to the entire scholarly community in open access.
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/313780
| Title: | Design of robust clocking circuit for moderate speed VLSI chip applications |
| Researcher: | Walunj, Rupali Ashok |
| Guide(s): | Kharate, Gajanan K |
| Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
| University: | Savitribai Phule Pune University |
| Completed Date: | 2019 |
| Abstract: | newline |
| Pagination: | |
| URI: | http://hdl.handle.net/10603/313780 |
| Appears in Departments: | Matoshri College of Engineering & Research Center, Nashik |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 01_title.pdf | Attached File | 41.98 kB | Adobe PDF | View/Open |
| 02_certificates.pdf | 519.6 kB | Adobe PDF | View/Open | |
| 03_declaration.pdf | 206.31 kB | Adobe PDF | View/Open | |
| 04_acknowledgement.pdf | 9.3 kB | Adobe PDF | View/Open | |
| 05_abstract.pdf | 12.55 kB | Adobe PDF | View/Open | |
| 06_list_of_tables & figures.pdf | 66.42 kB | Adobe PDF | View/Open | |
| 07_abbreviations.pdf | 92.73 kB | Adobe PDF | View/Open | |
| 08_contents.pdf.pdf | 56.3 kB | Adobe PDF | View/Open | |
| 09_chapter 1.pdf | 96.42 kB | Adobe PDF | View/Open | |
| 10_chapter 2.pdf | 412.84 kB | Adobe PDF | View/Open | |
| 11_chapter 3.pdf | 1.02 MB | Adobe PDF | View/Open | |
| 12_chapter 4.pdf | 1.7 MB | Adobe PDF | View/Open | |
| 13_chapter 5.pdf | 30.99 kB | Adobe PDF | View/Open | |
| 14_references.pdf | 194.91 kB | Adobe PDF | View/Open | |
| 80_recommendation.pdf | 67.72 kB | Adobe PDF | View/Open |
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