Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/313780
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dc.coverage.spatial
dc.date.accessioned2021-02-01T06:20:05Z-
dc.date.available2021-02-01T06:20:05Z-
dc.identifier.urihttp://hdl.handle.net/10603/313780-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDesign of robust clocking circuit for moderate speed VLSI chip applications
dc.title.alternative
dc.creator.researcherWalunj, Rupali Ashok
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideKharate, Gajanan K
dc.publisher.placePune
dc.publisher.universitySavitribai Phule Pune University
dc.publisher.institutionMatoshri College of Engineering and Research Center, Nashik
dc.date.registered2016
dc.date.completed2019
dc.date.awarded2019
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Matoshri College of Engineering & Research Center, Nashik

Files in This Item:
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01_title.pdfAttached File41.98 kBAdobe PDFView/Open
02_certificates.pdf519.6 kBAdobe PDFView/Open
03_declaration.pdf206.31 kBAdobe PDFView/Open
04_acknowledgement.pdf9.3 kBAdobe PDFView/Open
05_abstract.pdf12.55 kBAdobe PDFView/Open
06_list_of_tables & figures.pdf66.42 kBAdobe PDFView/Open
07_abbreviations.pdf92.73 kBAdobe PDFView/Open
08_contents.pdf.pdf56.3 kBAdobe PDFView/Open
09_chapter 1.pdf96.42 kBAdobe PDFView/Open
10_chapter 2.pdf412.84 kBAdobe PDFView/Open
11_chapter 3.pdf1.02 MBAdobe PDFView/Open
12_chapter 4.pdf1.7 MBAdobe PDFView/Open
13_chapter 5.pdf30.99 kBAdobe PDFView/Open
14_references.pdf194.91 kBAdobe PDFView/Open
80_recommendation.pdf67.72 kBAdobe PDFView/Open


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