Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/313703
Title: Performance Improvement of Certain Multiprocessor System on Chip for Low Power Applications
Researcher: KARTHICK, R
Guide(s): SUNDARARAJAN, M
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Bharath University
Completed Date: 2018
Abstract: In order to cope up with the functional operation criteria, our work concentrate on the percentage of indefinite values in the tests performed. A low power broadside test set is shown from a functional broadside set with the derivation of slanted load test cubes in BIST circuits. The twin effect of programmable truncated multiplication and fault-tolerant Digital Signal Processing (DSP) design is put on to reduce voltage beyond critical timing level. Effectiveness modulations possessions of truncated multiplication are examined for the betterment of fault tolerant designs, ranging the system operating voltage range and minimizing error correction burden. The lower power test schemes along with advanced Razor technique is implemented with the original Digital signal Processing. newlineThis work reflects the combined design of pre-coding, bit loading and receives filters for a MIMO wireless communication system. Together the sender and the receiver are supposed to match the frequency matrix exactly. It is already known that, for linear MIMO orthogonal transmission, transceivers are optimal for some facts such as huge mutual information. If the receiver applies the linear slightest mean squared error detector, an optimal transmission approach is to manipulate bit loading on an orthogonal sub channels. The transmission rate of the channel is adapted by assigns bits dynamically to the subchannels of the digital communication system. The process of comparing the decoding method is projected to enhance the design and its methodology. This provides better outcome related to the MMSE and bit rate while comparing with the conventional methods newline In this paper, the influence of the dynamic project scheduling process is surveyed. Out of-Order (OoO) implementation method showcase great assure for task-level parallelism in multiprocessor system-on-chip (MPSoC) designs. The advanced overall enactment can be conquered with the assist of a specific mapping of obligations onto the proper processors. Hence, to acquire this enactment, a P
Pagination: 
URI: http://hdl.handle.net/10603/313703
Appears in Departments:Department of Electronics and Communication Engineering

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chapter 3.pdf491.1 kBAdobe PDFView/Open
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title page.pdf156.01 kBAdobe PDFView/Open
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