1. Shodhganga@INFLIBNET
  2. Vellore Institute of Technology, Vellore
  3. School of Electronic Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/311596
Title: Area Efficient High Speed and Low Power CSLA and BCD Adders
Researcher: Ragunath G
Guide(s): Sakthivel R
Keywords: BCD Adders
CSLA
Low Power
University: VIT University
Completed Date: 2020
Abstract: newline
Pagination: 1-118
URI: http://hdl.handle.net/10603/311596
Appears in Departments:School of Electronic Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File46.52 kBAdobe PDFView/Open
02_declaration and certificate.pdf36.88 kBAdobe PDFView/Open
03_abstract.pdf28.01 kBAdobe PDFView/Open
04_acknowledgement.pdf24.3 kBAdobe PDFView/Open
05_table of contents.pdf23.62 kBAdobe PDFView/Open
06_list of figures.pdf25.86 kBAdobe PDFView/Open
07_list of tables.pdf20.67 kBAdobe PDFView/Open
08_list of terms abbreviations.pdf80.63 kBAdobe PDFView/Open
09_chapter 1.pdf130.12 kBAdobe PDFView/Open
10_chapter 2.pdf1.34 MBAdobe PDFView/Open
11_chapter 3.pdf381.04 kBAdobe PDFView/Open
12_chapter 4.pdf577.01 kBAdobe PDFView/Open
13_chapter 5.pdf594.12 kBAdobe PDFView/Open
14_chapter 6.pdf812.87 kBAdobe PDFView/Open
15_chapter 7.pdf21.45 kBAdobe PDFView/Open
16_references.pdf36.86 kBAdobe PDFView/Open
17_list of publications.pdf24.04 kBAdobe PDFView/Open
80_recommendation.pdf877.78 kBAdobe PDFView/Open
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