Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/309596
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dc.date.accessioned2020-12-21T12:16:12Z-
dc.date.available2020-12-21T12:16:12Z-
dc.identifier.urihttp://hdl.handle.net/10603/309596-
dc.description.abstractRapid growth in the semiconductor industry has reduced the size of the device, cost of an newlineIC and increased complexity as more and more features are being packed into an IC. The newlinetest data volume is always proportional to the size of an IC, and increases rapidly. The test newlinedata is essential to do structural testing of an IC to detect the faults introduced during newlinefabrication process of an IC. Large test data demands more ATE memory but ATE has newlinelimited. These forces upgrade to the ATE to increase memory capacity which is very newlineexpensive. Test data volume adds to the increased test application time and cost of testing newlinean IC. In this thesis, we addressed the issue of test data volume by introducing hybrid scan newlinecompression methods which are blend of scan and scan compression. These architectures newlinereduce the test data volume and contributing to the reduction in test application time and newlinetest cost. newlineThe hybrid scan compression architecture, excludes few scan cells from the compression newlinearchitecture and places them in the external chain(s). The scan cells excluded can be X newlinecapturing scan cells or scan cells requiring high probability of specified values in the test newlinepatterns. The Xs in unload test patterns causes test patterns inflation and loss of test newlinecoverage. The dependencies introduced by the scan compression also causes loss of test newlinecoverage and patterns inflation. The hybrid scan compression architecture addresses this newlineissue to reduce pattern count and improves test coverage. The algorithms to pick scan cells newlineto be excluded from the compression architecture and place them into an external scan newlinechains(s) in compression mode have been presented in this thesis. newlineOur experimental results show the huge reduction in test pattern count in excluding either newlineX-capturing scan cells or scan cells having highest probability of specified values newlineconsidering different algorithms proposed. The reduction in the pattern count achieved in newlineNSC method is up-to 78.14%, in Hybrid DFT up-to 80.34%, in AE method up-to 77.13% newlineand in X capturing scan cells exclusion up-to 78.90% based on the algorithms developed in newlinethe different experiments. Experimental results show no area overhead of the presented newlinemethods and can be used with any scan compression architecture exists in the industry. newline
dc.format.extent147 p
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleImproving compression for IC testing by analyzing intermediate patterns
dc.title.alternative
dc.creator.researcherPralhad Rao
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Software Engineering
dc.subject.keywordEngineering and Technology
dc.description.note
dc.contributor.guideRohit Kapoor and Chandrashekar Shastry
dc.publisher.placeBengaluru
dc.publisher.universityJain University
dc.publisher.institutionDept. of CS and IT
dc.date.registered2016
dc.date.completed2020
dc.date.awarded2020
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Dept. of CS & IT

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chapter1.pdf956.12 kBAdobe PDFView/Open
chapter2.pdf1.12 MBAdobe PDFView/Open
chapter3.pdf949.92 kBAdobe PDFView/Open
chapter4.pdf759.45 kBAdobe PDFView/Open
chapter5.pdf620.73 kBAdobe PDFView/Open
chapter6.pdf697.72 kBAdobe PDFView/Open
coverpage.pdf308.1 kBAdobe PDFView/Open
tableofcontents.pdf263.64 kBAdobe PDFView/Open


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