Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/307067
Title: Power Optimized Soft Error Hardened by Design of CMOS Latches and Flip Flops
Researcher: Satheesh Kumar S
Guide(s): Kumaravel S
Keywords: Radiation Hardened Techniques
Soft Error Flip-flops
Soft Error in Flip-flops
University: VIT University
Completed Date: 2019
Abstract: newline
Pagination: 1-121
URI: http://hdl.handle.net/10603/307067
Appears in Departments:School of Electronic Engineering

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01_title.pdfAttached File90.84 kBAdobe PDFView/Open
02_ certificate.pdf157.11 kBAdobe PDFView/Open
03_ declaration.pdf135.27 kBAdobe PDFView/Open
04_abstract.pdf61.67 kBAdobe PDFView/Open
05_content.pdf54.55 kBAdobe PDFView/Open
06_list of figures.pdf134.31 kBAdobe PDFView/Open
07_list of table, abbri,ack.pdf135.86 kBAdobe PDFView/Open
08_chapter-1.pdf2.53 MBAdobe PDFView/Open
09_chapter-2.pdf1.59 MBAdobe PDFView/Open
10_chapter-3.pdf9.85 MBAdobe PDFView/Open
11_chapter-4.pdf6.44 MBAdobe PDFView/Open
12_chapter-5.pdf9.85 MBAdobe PDFView/Open
13_chapter-6.pdf56.15 kBAdobe PDFView/Open
14_references.pdf82.05 kBAdobe PDFView/Open
15_list of publications.pdf59.4 kBAdobe PDFView/Open
80_recommendation.pdf9.99 MBAdobe PDFView/Open
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