Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/307067
Title: | Power Optimized Soft Error Hardened by Design of CMOS Latches and Flip Flops |
Researcher: | Satheesh Kumar S |
Guide(s): | Kumaravel S |
Keywords: | Radiation Hardened Techniques Soft Error Flip-flops Soft Error in Flip-flops |
University: | VIT University |
Completed Date: | 2019 |
Abstract: | newline |
Pagination: | 1-121 |
URI: | http://hdl.handle.net/10603/307067 |
Appears in Departments: | School of Electronic Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 90.84 kB | Adobe PDF | View/Open |
02_ certificate.pdf | 157.11 kB | Adobe PDF | View/Open | |
03_ declaration.pdf | 135.27 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 61.67 kB | Adobe PDF | View/Open | |
05_content.pdf | 54.55 kB | Adobe PDF | View/Open | |
06_list of figures.pdf | 134.31 kB | Adobe PDF | View/Open | |
07_list of table, abbri,ack.pdf | 135.86 kB | Adobe PDF | View/Open | |
08_chapter-1.pdf | 2.53 MB | Adobe PDF | View/Open | |
09_chapter-2.pdf | 1.59 MB | Adobe PDF | View/Open | |
10_chapter-3.pdf | 9.85 MB | Adobe PDF | View/Open | |
11_chapter-4.pdf | 6.44 MB | Adobe PDF | View/Open | |
12_chapter-5.pdf | 9.85 MB | Adobe PDF | View/Open | |
13_chapter-6.pdf | 56.15 kB | Adobe PDF | View/Open | |
14_references.pdf | 82.05 kB | Adobe PDF | View/Open | |
15_list of publications.pdf | 59.4 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 9.99 MB | Adobe PDF | View/Open |
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