High performance arithmetic circuit design for low power vlsi applications

Abstract

Growing demands and competitions in the market force the researchers to look for new designs Researchers have worked on this issue and adopted a suitable technique which has resulted in high speed and low power integrated chips Area power and delay form the important critical factors in any low power VLSI circuits For high performance chips addition and multiplication forms the basic requirement Adders form the basic newlinecomponent for all the circuit operations There is a need for the adder circuits in all digital applications So it is necessary to design a basic adder circuit which consumes low power and minimum delay Even basic multiplication consists of addition and adders are involved in it For high speed applications efficient adders should be newlinedesigned and the efficiency of the adder is determined by analyzing the factors of area power and delay The carry propagation delay problem is reduced by using carry select adder which is one of its important advantages So an efficient variable bit modified carry select adder having the combination of fast parallel prefix Brent Kung adder and D latch is designed Designing an efficient multiplier depends on designing an efficient adder. newline newline