Certain investigations on thermal aware testing and thermal aware test data compression for vlsi circuits

Abstract

Rapid progress in technology scaling has resulted in devices with billions of transistors Continuous scaling of the transistor feature size grows the probability of manufacturing defects in Integrated Circuits ICs Physical imperfections in the semiconductor manufacturing process demand testing of such ICs Manufacturers test their electronic products to scrap the faulty components to confirm that only defect free ICs make their way to the customer Testing of ICs is a big challenge due to several limiting factors The factors include high power consumption during test peak temperature and large volume of test data Many techniques have been presented to minimize the power newlineconsumption during testing Power aware test approaches cannot entirely evade the overheating problem High temperature arises in testing of modern System on Chip SoC and it may originate reliability problems Since poweraware approaches are unable to achieve the uniform distribution of heat power aware techniques cannot guarantee the thermal safety of ICs Thermalaware test generation is rarely found in the literature Hence an effort is taken in the present research to develop an algorithm for thermal aware test generation. newline newline