Investigations on phase frequency detector and charge pump circuits

Abstract

There is rapid development in the field of electronics and communication in recent years The Phase Locked Loop PLL system has versatile applications such as frequency synthesizers demodulators clock generation and clock recovery in microprocessors etc PLL is mainly employed for synchronization clock synthesis skew and jitter reduction in the modern wireless communication system One of the challenges in designing PLL is to enhance faster locking ability Hence there is a newlinerequirement of PLL to operate in the Giga Hertz GHz range with lesser lock time PLL is a mixed signal design consisting of both digital and analog sub modules The methodology used to design circuits range from transistor level to layout level The Phase Frequency Detector PFD circuit is the first sub module of a PLL It compares the input reference signal with the output signal of the Voltage Controlled Oscillator VCO circuit The output of the PFD circuit is fed to the Charge Pump CP circuit which is then connected to the loop filter. The loop filter is a Low Pass Filter LPF which integrates the error current and is connected to the VCO to generate a control voltage The VCO output signal and the reference signal are compared during which a lock situation is reached when the two clock signals are of same phase and frequency There are lot of challenges in designing every sub module of the PLL The dead zone problem in the PFD circuit and the current mismatch non-ideal effect in the CP circuit directly affect the performance of the PLL. newline newline