Implementation of Convolution and Multipliers in VLSI using Vedic Mathematics

Abstract

With the advancements in VLSI technology, it is desirable that the arithmetic newlinesystem should take less processing time and power consumption for calculation. newlineWith this concept in mind, the present research work deals with designing of newlineimproved multipliers. In digital signal processing (DSP), convolution is a basic newlineoperation. Numerous research works have already been reported in literature to newlinedesign a convolution circuit. A new technique of convolution which is improved newlineversion in terms of speed and power consumption has been reported here. Among newlineother algorithms used in DSP, Fast Fourier Transform (FFT) is used to calculate newlineDiscrete Fourier Transform (DFT) in less time. In FFT the most time consuming newlineoperation is complex multiplier. So, it arises the need of improved complex newlinemultiplier for the fast calculation of DFT. In this work, a complex multiplier is newlinepresented, which satisfies the need of faster calculation. newlineVedic mathematics was rediscovered from the ancient Indian scriptures newlinebetween 1911 and 1918 by Sri Bharati Krishna Tirthaji (1884-1960) and on the basis newlineof the same, different multipliers based on Vedic mathematics sUTras, namely, newlineUrdhva Tiryagbhyam (UT) SUTra, Nikhilum (NM) SUTra, Anurupyena (AN) newlineSUTra using CMOS topology were presented. The present work deals with the newlinedesigning of a 2 x 2, 4 x 4, 8 x 8, 16 x 16 and 32 x 32 bit UT, NM and AN newlinemultipliers based on CMOS and McCMOS topologies. It has been observed that the newlinedesigned 32 x 32 NM McCMOS multiplier dissipates a power of 0.556 mW and newlinepropagation delay of 27.82 nsec which is far better when compared with the reported newlinesimilar circuit designed using CMOS topology. It has also been shown that for 4x 4 newlinebit UT multiplier consumes less power in comparison to AN and NM multipliers. newlineAlso, for 8 x 8 and 16 x 16 bit multipliers, NM multiplier consumes less power, newlinewhereas for 32 x 32 bit multiplier, AN consumes less power. newline newline