Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/304584
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dc.coverage.spatial
dc.date.accessioned2020-10-28T08:48:26Z-
dc.date.available2020-10-28T08:48:26Z-
dc.identifier.urihttp://hdl.handle.net/10603/304584-
dc.description.abstractThe objective of this research is to a develop floorplanning algorithm that facilitates newlinethe physical design methodologies for integrated circuit (IC) designs using Multiple newlineSupply Voltages (MSV) and implementing in various design stages to evaluate the improvements newlinein the performance. newlineFloorplanning in MSV ICs is one of the last challenges in back-end process as it newlinerequires compatibility in satisfying voltage island and fixed outline constraints. First, a newlinemodified floorplanning technique for MSV designs is developed. Next, the algorithm newlineis implemented to a commercial EDA environment under various fixed aspect ratios, newlinealong with a study on how the proposed algorithm mitigate to satisfy voltage island newlineconstraints. Finally, the algorithm is performed to satisfy both fixed outline and voltage newlineisland constraints. newlineVoltage drop reduction in the power ground network has become a challenging problem newlinein the modern multiple supply voltage designs. An effective P/G network design newlineand floorplanning of modules produce a quality power plan in the layout. Hence, this newlineresearch proposes an iterative MSV floorplanning methodology that performs modifications newlinein the skewed binary tree representation to satisfy the voltage island constraint newlineand produce an IR drop-aware quality layout newline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDevelopment and Optimization of Multiple Supply Voltage Floorplanning Algorithms for Modern ICs
dc.title.alternative
dc.creator.researcherSrinath.B
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideAruna Priya.P
dc.publisher.placeKattankulathur
dc.publisher.universitySRM University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered
dc.date.completed2019
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

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80_recommendation.pdfAttached File132.41 kBAdobe PDFView/Open
abstract.pdf77.18 kBAdobe PDFView/Open
acknowledgement.pdf77.21 kBAdobe PDFView/Open
chapter 1.pdf384.51 kBAdobe PDFView/Open
chapter 2.pdf264.66 kBAdobe PDFView/Open
chapter 3.pdf763.61 kBAdobe PDFView/Open
chapter 4.pdf1.77 MBAdobe PDFView/Open
chapter 5.pdf1.33 MBAdobe PDFView/Open
chapter 6.pdf1.91 MBAdobe PDFView/Open
chapter 7.pdf78.73 kBAdobe PDFView/Open
declaration.pdf78.85 kBAdobe PDFView/Open
list of publications.pdf76.15 kBAdobe PDFView/Open
preliminary pages.pdf178.44 kBAdobe PDFView/Open
references.pdf124.66 kBAdobe PDFView/Open
title.pdf82.58 kBAdobe PDFView/Open
vitae.pdf75.71 kBAdobe PDFView/Open


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