Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/303285
Title: Design of built in self test for analog to digital converter with static error modeling and calibration
Researcher: Senthil Sivakumar M
Guide(s): Joy Vasantha Rani S P
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
Digital converters
Built-In Self-Test
Signal generator
University: Anna University
Completed Date: 2019
Abstract: Analog to Digital Converter ADC is a most widely used mixed signal circuit in DSP processors to convert the real time signals into digital data Testing the accuracy of an ADC is an important requirement in the mixed signal devices since it has a capacity to decide the perfectness of the complete system Conventionally the mixed signal circuits like an ADC are tested using DSP based mixed signal tester with an arbitrary waveform generator and a signal digitizer Use of an off chip test equipment increases the test cost test time and complexity of the testing due to high integration density limited accessibility of the internal components and the requirement of high linearity and resolution Built In Self Test BIST is the popular on chip testing method to diagnose and isolate the catastrophic and parametric faults present in the data conversion In BIST technique test stimuli generation and response analysis circuits are integrated entirely on-chip through built in hardware Neither external test stimulus generator nor external digital signal processing unit is required resulting in low cost and low testing time The BIST based testing system requires the linear ramp signal generator ADC under test fault analyzer and a control circuit Area overhead test time power dissipation are the important requirements in an on chip testing since BIST is an additional circuit in the hardware In this research work the data conversion structure based digital BIST techniques have been proposed to test the static characteristics of an ADC through linear ramp signal generation and output response analysis. newline
Pagination: xx,212p.
URI: http://hdl.handle.net/10603/303285
Appears in Departments:Faculty of Information and Communication Engineering

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04_acknowledgements.pdf4.27 kBAdobe PDFView/Open
05_contents.pdf8.49 kBAdobe PDFView/Open
06_list_of_tables.pdf4.74 kBAdobe PDFView/Open
07_list_of_figures.pdf9.19 kBAdobe PDFView/Open
08_list_of_abbreviations.pdf17.06 kBAdobe PDFView/Open
09_chapter1.pdf370.27 kBAdobe PDFView/Open
10_chapter2.pdf66.63 kBAdobe PDFView/Open
11_chapter3.pdf245.72 kBAdobe PDFView/Open
12_chapter4.pdf2.1 MBAdobe PDFView/Open
13_chapter5.pdf668.03 kBAdobe PDFView/Open
14_chapter6.pdf3.66 MBAdobe PDFView/Open
15_conclusion.pdf50.25 kBAdobe PDFView/Open
16_references.pdf49.27 kBAdobe PDFView/Open
17_list_of_publications.pdf16.36 kBAdobe PDFView/Open
80_recommendation.pdf117.6 kBAdobe PDFView/Open
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