Investigation on area efficient architecture for OFDM transceiver

Abstract

In recent times the development of wideband wireless communication system has been increased due to customer interest towards high speed wireless communication Orthogonal Frequency Division Multiplexing OFDM transceiver design is a pivotal task The OFDM transceiver used to increase the data transmission faster by excellence of its Multi carrier modulation and targets high spectral efficiency The Fast Fourier Transform FFT and Inverse Fast Fourier Transform IFFT algorithms play a vital role in OFDM system which requires more hardware complexity The structure of FFT processor depends on the selection of radix algorithms The choice of small radix in the FFT processor results in simple butterfly structures Meanwhile the numbers of twiddle factor multiplications are reduced using higher radix values Hence in FFT processors Multi radix algorithms are desirable to minimize the hardware complexity An improved area and power efficient FFT IFFT processor is proposed for OFDM transceiver In the proposed work a radix 25 algorithm based 512 point FFT IFFT Processor having Multi path delay structure with eight parallel data paths is considered for implementation newline