Design and experimental implementation of low power four bit analog to digital converters for automotive applications

Abstract

Power Consumption is one of the important design restrictions in the modern day Very Large Scale Integration VLSI technology For the portable electronics systems which are mostly powered by batteries over their entire lifetime the low power consumption is dominant. Hence power consumption is given more priority than other performance metrics while designing System on Chip SoC devices In this digitized world there is a need of Analog to Digital Converter ADC in the SoC architectures ADCs are indispensable and ubiquitous in the design of digital Integrated Circuits ICs because ADCs act as interface between the real analog world and the digital domain The design of low power area efficient and low output offset voltage comparator is the basic necessity for various design and implementation of power and area efficient ADC designs Among various comparator designs dynamic comparators are highly recommended in the ADC design due to their negligible amount of static power dissipation In addition to comparators other basic building blocks are also required in the design of ADC architectures. There are several types of ADCs available to satisfy the requirement of electronic applications Flash ADC Successive Approximation Register (SAR) ADC and pipelined ADC are the commonly used architectures. newline