Cross Talk Analysis in Carbon Nanotube Based VLSI Interconnects

Abstract

With advanced technology nodes, large number of functionalities is integrated in a Very Large Scale Integration (VLSI) chip. Thus, the density of long interconnects is increased exponentially that connect millions of active devices on a chip, is posing a serious bottleneck in terms of substantial capacitive and inductive couplings. Hence there appears a dire need to search a potential material for future generation of VLSI interconnects that will be capable of exhibiting minimized propagation delay, power dissipation and crosstalk effects. The present work explores the possibilities of alternative interconnect material for future VLSI interconnects. The most promising alternative for copper interconnects turns out to be Carbon Nanotube (CNT).A comparative analysis of the propagation delay, power dissipation, cross-talk induced noise voltage and its frequency spectrum in CMOS inverter driven global interconnects of SWCNT bundle and copper has been presented. The single interconnect as well as capacitively coupled interconnects are represented by the and#960;-equivalent circuit of distributed RLC-model. The Driver-Interconnect-Load (DIL) model [15] of distributed RLC circuit is used for the mutually coupled interconnects. An Alpha power law model [129] is used for representing the transistor in the CMOS inverter (driver). Influence of separation between adjacent tubes of various lengths and tube diameters, on delay and power dissipation in Single Walled Carbon Nanotube (SWCNT) bundle interconnect has been analyzed at 32nm and 22nm technology nodes. The main aim of this investigation is to optimize separation distance(x) between adjacent SWCNT and tube diameter (d) for better performance. The output waveform is analytically determined using CMOS inverter driven and#960;-equivalent RLC circuit of SWCNT bundle and copper interconnect. The results are compared with SPICE simulation results at same technology nodes.