Area efficient low power router design for network on chip NOC architecture with optimized topology

Abstract

Network on Chip NoC is a modern technique for the System on Chip SoC design The NoC technique can increases the system performance and brings the networking technique to on chip system communications compared to the conventional bus systems Intra chip communication in the Giga scale sizes of chip is an extreme challenge for downscaling of silicon and multiprocessor on chip system design For this reason it is familiar in deep submicron era Intra chip communication characterizes various applications in signals and sensor systems In giga scale level it examines the performance power consumption and flexibility of the design By sacrificing the chip area and with enhanced design techniques the latest enrichment in the bus for intra chip communication enables to deal with chip size scaling and modular limitations With the aim of limiting the adverse effects of chip scaling to increase the performance of the chip and avoiding the design complexity in the on chip communication process an innovative approach called Network on chip is initiated The NoC attracts on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way The principle intention pursued is to obtain advanced bandwidth when compared to standard on chip bus architectures Lowering the NoC power is vital for scaling up the wide variety of nodes in future many core systems NoC have the advantages of bus based systems over traditional one The design space is very large comparing to bus based approaches It can be implemented in many organizations due to its communication infra structure The benefit of using NoC is to reduce power consumption and latency overheads of routers newline