Certain investigations on performance analysis of VLSI architectures for arithmetical applications

Abstract

newlineThis thesis presents the design and implementation of a high performance hybrid logic technique with increased noise robustness and reduced leakages The speed and overhead area are the primary factors for the manufacturing industry leading to the invention of clocked logic styles The main parameters to design any kind of digital circuit technology with an effective trade off between these parameters are power consumption noise immunity the speed of operation area and cost Hybrid logic has become the choice to design high speed application circuits because of its high speed and low overhead area The issues involved are high power consumption and high noise sensitivity Therefore the hybrid methodology needs to be developed to meet the requirements by overcoming the above disadvantages that led to broad opportunities for diverse research in this area The findings of this research therefore need to be able to deal efficiently with primary design parameters In addition the designed circuit needs to show a high level of noise robustness In this thesis a limited number of techniques are proposed for managing noise and sub threshold leakage In the hybrid logic techniques the impact of signal integrity problems is studied Moreover the overall performance of the proposed hybrid techniques has been improved despite several restrictions in this work having subjected to process corner analysis and noise analysis newline newline