Towards evolvable fault tolerant Digital circuits

Abstract

newlineThe automated design technique which uses Evolutionary newlineAlgorithms that employ the Darwinian principles of evolution for the design of newlineelectronic circuits is known as Evolvable Hardware EHW This thesis newlineaddresses the design of fault tolerant digital circuits in an EHW framework and newlineproposes methods to increase the scalability of such evolutionary techniques newlineThis is achieved by exploiting the inherent redundancy of the evolutionary newlineTechniques The first part of the thesis proposes the n Version Genetic Algorithm newlinebased Fault Tolerant nVGAFT framework This is built on the multiple newlineversions approach where different versions of a circuit that are functionally newlineidentical but structurally different are evolved Each of these versions uses the newlineredundant components in the evolved solution to provide fault correction for newlineother versions This framework is also used for on line testing of the newlinecomponents by cyclically downloading the versions and exercising the newlinecomponents This framework is then enhanced to cover unknown circuits and the newlineGeneric n Version GA based Fault Tolerant GnVGAFT framework is newlineProposed This incorporates a redistribution algorithm to reduce the evolution newlineTime and a fault isolator to reduce the fault correction time Simulation results newlinefor various benchmark circuits and a proof of concept hardware newlineimplementation on a Field Programmable Gate Array FPGA are provided newline