Certain investigations on power and ground bounce mitigation in nanoscale VLSI circuits

Abstract

In this modern era the challenge for chip designers is to maintain a long enough battery life in portable devices such as smart phones tablet computers etc as power consumption increases with enhanced functionality and operating frequency Excessive power consumption is a major hindrance to the advancement of nanoscale Complementary Metal Oxide Semiconductor CMOS Very Large Scale Integration VLSI circuits Leakage currents are important sources of power consumption in modern nanoscale VLSI circuits Hence suppressing leakage currents in large scale integrated circuits is essential for achieving extended battery life and facilitating the proliferation of portable electronic devices Mode transition noise is another important reliability issue in nanometer regime with shrinking noise margins Significant ground bounce is produced when circuit blocks transits from sleep mode to active mode Due to this noise, the active blocks may latch a wrong state if the voltage due to ground bounce is higher than the noise margin of the circuit Power gating is the most commonly used power and ground bounce suppression technique in state-of-the-art integrated circuits The basic strategy of power gating is to provide two power modes: a sleep mode and an active mode Power gating structures are designed such that it makes the circuit blocks to switch between these modes at and in the appropriate manner to maximize power savings while minimizing the impact to performance The research work in this thesis mainly focuses on the design of power gating techniques with superior performance compared to conventional techniques newline