Investigations on upgrading power reduction techniques for VLSI based computational circuits

Abstract

The popularity and explosive growth of portable electronics motivate the designers to drive towards system designs with a smaller silicon area higher speeds and higher reliability Last decade onwards the emphasis of the system design in VLSI has shifted from high speed to low power However electronic portable devices such as Personal Digital Assistants notebook computers and mobile phones require enormous volume of data processing to be done For such multimedia devices the prime goal of using low power design is to curtail the total power dissipation of the system to preserve the reliability of the integrated circuit chips The main sources of power dissipation are dynamic and static power dissipation In deep sub-micron circuits leakage power in static power dissipation has become an increased proportion compared to dynamic power dissipation For CMOS technologies below 65nm 50 percentage of total power consumption arises from leakage current During the last few years various low power design techniques have been implemented to reduce leakage power at multiple abstraction levels There are various types of leakage current out of which sub-threshold leakage current is predominant in deep sub-micron devices Initially a search was done on circuit level design methods to reduce the active mode or static mode of power dissipation This search revealed the achievement of reduction in static power dissipation at the expense of active power dissipation However both types of power dissipation require reduction in order to have reduced total power dissipation in deep sub-micron designs newline