Multi constraint shortest path optimization using metaheuristic algorithms in asynchronous network on chip

Abstract

Network-On-Chip (NOC) offers itself to be a suitable interconnection structure and as a viable alternative for system-on-chip, and hence is employed in Very-Large-Scale Integration (VLSI) design. An asynchronous Network-On-Chip (ANOC) design has low energy consumption because of the absence of the clock. However, obtaining optimal path routing in an ANOC poses computational complexities. There are two major design challenges for any interconnection network: its overall cost and its performance. The performance of the network is dependent upon the topology configuration adopted by the network and employed by the network s routing algorithm. ANOC design primarily depends upon the topology, switching mechanism, and the routing algorithm. The Hopfield Neural Network (HNN) asynchronous mesh topology is used in this research. To optimize the routing method, several algorithms have been coupled to the shortest path problem. Existing techniques like Dijikstra, Floyd-Warshalls, and Bellman Ford algorithms do not guarantee feasible solutions when subjected to complex search space, since they are unable to meet the requirements of operational efficiency for a highly dynamic topology. In this work, the multi constrained shortest optimal paths are determined by employing five contemporary optimization techniques like Particle swarm optimization, Ant colony optimization, Firefly optimization, Cuckoo search optimization and Harmony search optimization. All the five algorithms are simulated and studied. newline