1. Shodhganga@INFLIBNET
  2. Manipal Academy of Higher Education
  3. Manipal Institute of Technology
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/297921
Title: Design of low power delay product multiplier and divider units
Researcher: Chaitanya C V S
Guide(s): Venkateswaran,P R and Prasad,Keerthana
Keywords: Computer Science
Computer Science Information Systems
Engineering and Technology
University: Manipal Academy of Higher Education
Completed Date: 2020
Abstract: Available
Pagination: 119 p.
URI: http://hdl.handle.net/10603/297921
Appears in Departments:Manipal Institute of Technology

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File181.25 kBAdobe PDFView/Open
02_ certificates.pdf324.14 kBAdobe PDFView/Open
03_ abstract.pdf238.84 kBAdobe PDFView/Open
04_declaration.pdf352.72 kBAdobe PDFView/Open
05_ acknowledgement.pdf85.11 kBAdobe PDFView/Open
06_ content.pdf240.03 kBAdobe PDFView/Open
07_list_of_tables.pdf121.94 kBAdobe PDFView/Open
08_ list_of_figures.pdf126.53 kBAdobe PDFView/Open
09_ abbreviations.pdf236.07 kBAdobe PDFView/Open
10_ chapter_1_introduction.pdf502.07 kBAdobe PDFView/Open
11_ chapter_2_literature review.pdf968.81 kBAdobe PDFView/Open
12_ chapter_3_binary multiplier using carry pre-computation.pdf1.46 MBAdobe PDFView/Open
13_ chapter_4_binary divider using divide and conquer approach.pdf1.49 MBAdobe PDFView/Open
14_ chapter_5_arithmetic unit with integrated multiplier and divider.pdf678.66 kBAdobe PDFView/Open
15_ chapter_6_conclusion.pdf154.61 kBAdobe PDFView/Open
16_ bibliography.pdf711.14 kBAdobe PDFView/Open
80_recommendation.pdf181.25 kBAdobe PDFView/Open
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