Digital filter design using evolvable Hardware chip for image Enhancement

Abstract

Image enhancement is an important image preprocessing technique newlineand it allows an encoded image to be reconstructed progressively in newlineterms of fidelity detail or resolution Specific Regions of Interest newlinecan also be specified and encoded with greater detail Random access newlineto the compressed image is possible allowing certain areas to be newlinedecoded without the need to decode the entire image While some newlineapplications such as enhancing poor quality satellite images will require newlineimage enhancement to be implemented in software other image enhancement newlineschemes to be ported inside a digital camera for example will require the newlinealgorithm to be implemented in hardware A hybrid coprocessing newlineapproach is also possible using hardware for parts of the newlinealgorithm that are computationally intensive and software for the parts that newlineare difficult to implement in a hardware environment newlineIn this thesis a VHDL implementation of the image enhancement newlinefilter is presented suitable for implementation on an FPGA In the first phase newlineof this work the design presented has been verified in simulation The newlinesecond phase involves programming an FPGA with these VHDL modules for newlinecomplete system integration The VHDL hardware description language is newlineused to develop digital designs that can perform this relevant processing The newlineVHDL implementation once programmed into the FPGA is intended newlineto replace that part of the software implementation It is estimated that newlinewhen implemented in hardware the VHDL module GA processor VRC newlinecould perform its computation approximately 180 times faster compared to newlinethe time taken by conventional image enhancement filters newline newline