Design and performance evaluation of multistage interconnection networks

Abstract

Most of today‟s computing systems, ranging from large parallel systems and high performance clusters to a single chip System-on-Chip (SoC), that need communication among multiple constituents, use interconnection networks. Examples of interconnection networks include the internal buses in VLSI circuits, telephone switches and networks, networks for parallel/distributed computing systems (including vector supercomputers, multi-computers, multiprocessors, cluster/network of workstations), LAN, MAN, WAN, and networks for industrial applications and electronic devices. Interconnection networks are one of the prime factors in determining the performance of such architectures, affecting the message latency, bandwidth, routing complexity, switching structure, system scalability, fault-tolerance and overall cost. A bottleneck in these parallel computing systems is the communication between processors. Therefore, the performance of interconnection networks is a critical issue in parallel computing. This has been a major driving force for the research of inter-connection networks. The study of interconnection networks in parallel computing system includes the design, performance and cost issues. Therefore, a designer is faced with several tradeoffs between performance, reliability and cost while designing interconnection networks for multiprocessor systems. The overall performance and cost-effectiveness of the existing multistage interconnection networks decreases as the network size increases, and the growth in faults has a deteriorating effect on the routing of packets from input to output nodes. Consequently, a demand for newer design interconnection networks subsists for sustained fault-tolerant operation.