Energy Efficient 4G LTE Turbo Decoder for High Speed Wireless Communication

Abstract

Turbo Encoder and Decoder are two important blocks of Long Term Evolution (LTE) newlinesystems, as they address the data encoding and decoding in a communication system. In newlinerecent years the wireless communication has advanced to suite the user needs. LTE network newlinesystems are standardized with high speed data transmission up to hundreds of Mbps. newlineNowadays smart phones and portable electronic gadgets become part of our life routine. The newlinerecent researches provide the global solution in terms of computation and miniaturization of newlinedevices to meet the end user requirements. But still there is inadequate advances are newlinehappening in the area of power optimization to convene the cutting edge requirements. newlineThe work is highly focused on optimizing the power consumption in high speed wireless newlinecommunication networks like 4G LTE and deep space communication networks. The power newlineoptimization can be achieved by proposing early termination of decoding iteration where newlinenumber of iterations is made adjustable which stops the decoding as it finishes the process. newlineClock gating technique is used at the Branch Metric Unit (BMU), State Metric Unit (SMU) newlineand ADD-Compare-Select unit (ACS) of RTL level to avoid the unnecessary clock given to newlinesequential circuits; here clock supplies are major source of power dissipation. newlineThis proposal is towards model, design and Application Specific Integrated Circuit (ASIC) newlineimplementation to optimize turbo decoder using Complementary Metal Oxide Semiconductor newline(CMOS) standard cell library. A software reference model for turbo encoder and decoder are newlinemodelled using MATLAB Simulink. Performance of the proposed model is estimated and newlineanalyzed on various parameters like frame length, number of iterations and channel noise. newlineRegister Transfer Language (RTL) model for Encoder and Decoder can be developed using newlineVerilog Hardware Description Language (HDL) and synthesized. The ASIC implementation newlinewith various performance parameters like power and speed are considered to evaluate the newlineproposed algorithm on decoder blocks. newlineIn this work, it is proposed to examine Error in communication channel, channel coding, newlinedecoding algorithms for turbo decoder. The current research involved in analysis of many newlinealgorithms such as log-MAP and max log-MAP algorithms for turbo codes. Turbo Decoder newlinewith max log-MAP decoding algorithm is modelled from algorithmic level, concentrating on newlinethe functional correctness along with the implementation of architecture. The performance of newlinea system is affected due to the numbers of parameters, in that to highlight a few channel newlinenoise, type of decoding and encoding techniques, type of interleaver, number of iterations and newlineframe length on the Matlab Simulink platform. The hardware of the Turbo Decoder is newlinemodelled in Verilog HDL, simulated in ModelSim, and synthesized using Xilinx ISE to newlineimplement the design on Virtex 5 FPGA platform. The same design is ported on the newlineElectronic Design Automation (EDA) tool like cadence and top-down design methodology is newlinefollowed for the front end design flow newline