1. Shodhganga@INFLIBNET
  2. KIIT University
  3. School of Computer Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/287353
Title: Development and analysis of new topologies on cascaded multi level inverter with reduced device count
Researcher: Nanda L.
Guide(s): Dasgupta A. and Rout U.K.
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
University: KIIT University
Completed Date: -
Abstract: Abstract is available. newline
Pagination: xxii,133p.
URI: http://hdl.handle.net/10603/287353
Appears in Departments:School of Computer Engineering

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01_title.pdfAttached File143.73 kBAdobe PDFView/Open
02_certificate.pdf144.18 kBAdobe PDFView/Open
03_dedication.pdf92.63 kBAdobe PDFView/Open
04_acknowledgements.pdf55.95 kBAdobe PDFView/Open
05_declaration.pdf121.32 kBAdobe PDFView/Open
06_abstract.pdf56.02 kBAdobe PDFView/Open
07_table of contents.pdf88.81 kBAdobe PDFView/Open
08_list of figures.pdf150.94 kBAdobe PDFView/Open
09_list of tables.pdf68.69 kBAdobe PDFView/Open
10_list of abbreviations.pdf59.11 kBAdobe PDFView/Open
11_list of symbols.pdf55.03 kBAdobe PDFView/Open
12_chapter 1.pdf153.71 kBAdobe PDFView/Open
13_chapter 2.pdf950.95 kBAdobe PDFView/Open
14_chapter 3.pdf337.78 kBAdobe PDFView/Open
15_chapter 4.pdf606.52 kBAdobe PDFView/Open
16_chapter 5.pdf924.28 kBAdobe PDFView/Open
17_chapter 6.pdf636.35 kBAdobe PDFView/Open
18_chapter 7.pdf130.52 kBAdobe PDFView/Open
19_references.pdf230.67 kBAdobe PDFView/Open
20_appendices.pdf234.83 kBAdobe PDFView/Open
21_list of publications.pdf193.16 kBAdobe PDFView/Open
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