Investigations on power estimation and power delay optimization in certain digital vlsi circuits

Abstract

The advancement in Very Large Scale Integration VLSI newlinetechnology has allowed the integration of more and more functionalities onto newlinea single chip Precisely estimating power for complex digital VLSI circuits at newlinean earlier stage can save the complicated and expensive redesign task which newlinewould occur if power constraints in the specifications are violated Portable newlinesystems like notebook computers laptops mobiles and Personal Digital newlineAssistants PDA demand reduced power consumption to enhance the battery newlinelifetime There is a steady growth in the operating frequency of newlines and Digital Signal Processors DSPs in daytoday newlinelife This causes increased power dissipation which inturn can create thermal newlinehot spots This may lead to reduced circuit reliability and life expectancy newline newline