Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/284466
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dc.coverage.spatial
dc.date.accessioned2020-03-23T11:49:29Z-
dc.date.available2020-03-23T11:49:29Z-
dc.identifier.urihttp://hdl.handle.net/10603/284466-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDesign Simulation and Synthesis Of Combinational and Sequential Logic Systems Using Reversible Logic
dc.title.alternative
dc.creator.researcherSrinivasa Rao N
dc.description.note
dc.contributor.guideSathyanarayana P
dc.publisher.placeTirupati
dc.publisher.universitySri Venkateswara University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered10-12-2015
dc.date.completed2017
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics & Communication Engineering

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01_title.pdfAttached File499.06 kBAdobe PDFView/Open
02_certificate.pdf328.22 kBAdobe PDFView/Open
03_declaration.pdf274.66 kBAdobe PDFView/Open
04_acknowledgement.pdf12.71 kBAdobe PDFView/Open
05_table of contents.pdf287.61 kBAdobe PDFView/Open
06_abbrevations.pdf104.92 kBAdobe PDFView/Open
07_list of tables.pdf110.78 kBAdobe PDFView/Open
08_list of figures.pdf120.75 kBAdobe PDFView/Open
09_chapter_01.pdf1.01 MBAdobe PDFView/Open
10_chapter_02.pdf98.9 kBAdobe PDFView/Open
11_chapter_03.pdf1.05 MBAdobe PDFView/Open
12_chapter_04.pdf1.11 MBAdobe PDFView/Open
13_chapter_05.pdf1.15 MBAdobe PDFView/Open
14_chapter_06.pdf90.97 kBAdobe PDFView/Open
15_bibliography.pdf89.29 kBAdobe PDFView/Open
16_appendix_a.pdf533.33 kBAdobe PDFView/Open
17_appendix_b.pdf917.79 kBAdobe PDFView/Open
18_publications.pdf64.57 kBAdobe PDFView/Open
19_abstract.pdf159.95 kBAdobe PDFView/Open


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