Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/283375
Title: An empirical study on performance and speed up in fpga based network intrusion detection
Researcher: Armstrong joseph J
Guide(s): Reeba korah
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
Fpga
Speed up
University: Anna University
Completed Date: 2019
Abstract: Network Intrusion Detection System (NIDS) has been emerging as newlinean important detection tool for the impact of malicious threats and newlinevulnerabilities in network security. It is a software application that monitors a newlinenetwork or system for malicious activity or policy violations. Snort is an newlineintrusion detection system that scans all the packets in a network and newlinecompares them against signatures specified in payloads of known malicious newlinethreats. Performance of snort can be reduced by processing large database of newlineinput text. It could be increased using FPGA hardware design through parallel newlineprocessing. In this research, a robust methodology for improving newlineperformance and speedup of NIDS has been presented. It can be seen as a newlinevital step in the development of network security. What is presented is a new, newlinefast, and fully performance and speedup algorithm developed by string newlinematching and editing bitmap files approach respectively for efficient Network newlineIntrusion Detection System.First, the performance is calculated by throughput per area. Here, newlinethe throughput is designed to adopt working frequency multiplied by number newlineof bits per cycle. It is then implemented in a hardware based NIDS using newlineFPGA and is designed as the function of software based NIDS (Snort), in newlineorder to get a better performance. String matching is achieved using the newlinebuffered input Boyer-Moore algorithm to get parallel input in content newlinematching on IDEs. Efficiency of IDS and their effect on the performance are newlineconsidered. The proposed performance is obtained using Xilinx Vivado newline newline
Pagination: xiv, 119p.
URI: http://hdl.handle.net/10603/283375
Appears in Departments:Faculty of Information and Communication Engineering

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02_certificate1.pdf69.54 kBAdobe PDFView/Open
03_certificate2.pdf97.49 kBAdobe PDFView/Open
04_certificate3.pdf83.29 kBAdobe PDFView/Open
05_abstracts.pdf9.52 kBAdobe PDFView/Open
06_acknowledgements.pdf91.53 kBAdobe PDFView/Open
07_contents.pdf108.89 kBAdobe PDFView/Open
08_listoftables.pdf7.65 kBAdobe PDFView/Open
09_listoffigures.pdf109.11 kBAdobe PDFView/Open
10_listofabbreviations.pdf9.12 kBAdobe PDFView/Open
11_chapter1.pdf256.55 kBAdobe PDFView/Open
12_chapter2.pdf218.23 kBAdobe PDFView/Open
13_chapter3.pdf441.56 kBAdobe PDFView/Open
14_chapter4.pdf557.78 kBAdobe PDFView/Open
15_chapter5.pdf120.85 kBAdobe PDFView/Open
16_chapter6.pdf544.04 kBAdobe PDFView/Open
17_appendices.pdf161.21 kBAdobe PDFView/Open
18_conclusion.pdf17.76 kBAdobe PDFView/Open
19_references.pdf151.53 kBAdobe PDFView/Open
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