Certain investigations on the power efficient delay buffer design in pipelined fft processor using micrologic elements

Abstract

Digital signal processing based Integrated Circuits (ICs) are being fabricated for different consumer products. The ICs are to be efficient and should consume less power. Due to the increasing features in consumer products the designs are to be with high device density, low power and high speed. The reliability is a main problem in Very Large Scale Integration due to discrete components. So system on chip architectures has emerged to improve the efficiency, speed and power consumption. New design methodologies have evolved in recent years. The evolution in VLSI has extended towards devices, circuits and systems. The earlier methods use Delay buffer design in pipelined FFT Processor such as SRAM/Register File-based delay buffer design, Shift registers, Pointer based delay buffers, Delay buffers with Gated clocks and Double Edge Triggered Flip-Flops and Delay buffers replaced by Shields. When Shift Register are highly complex for one bit storage, it cannot be used for long delay buffers, the SRAM/Register based delay buffer design suffer from high power consumption. The existing delay buffer design using Muller C-element Gated clock with Gated Driver tree and Look ahead Clock gating techniques are proved to be efficient in reducing the Propagation delay and Power consumption, but did not produce good throughput because of Metastability and difference in threshold voltages for different devices. As an alternative this work presents the investigation, design and development of a Micrologic Elements (MLEs) based FFT blocks. The presented power efficient delay buffers provide high fan-out, low power dissipation, high speed and high noise immunity. Previous research works were investigated, analyzed and implemented. Based on the problem, the research is focussed on designing a delay buffer for the pipelined FFT architecture newline