1. Shodhganga@INFLIBNET
  2. Symbiosis International University
  3. Faculty of Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/283144
Title: Performance Efficient Network on Chip Interconnects for Mesh Topology using Field Programmable Gate Array
Researcher: Shahane Priti Mandar
Guide(s): Pisharoty Narayan
Keywords: Communication Architecture
Field Programmable Gate Array
FPGA
Mesh Topology
MPSoC
Multiprocessor System on Chip
Network on Chip
NoC Router
University: Symbiosis International University
Completed Date: 2019
Abstract: newline
Pagination: 103 p.
URI: http://hdl.handle.net/10603/283144
Appears in Departments:Faculty of Engineering

Files in This Item:
File Description SizeFormat 
acknowledgment.pdfAttached File413.25 kBAdobe PDFView/Open
annexure a.pdf306.17 kBAdobe PDFView/Open
annexure b.pdf222.75 kBAdobe PDFView/Open
annexure c.pdf218.66 kBAdobe PDFView/Open
certificate.pdf424.98 kBAdobe PDFView/Open
chapter 1.pdf406.8 kBAdobe PDFView/Open
chapter 2.pdf821.1 kBAdobe PDFView/Open
chapter 3.pdf1.34 MBAdobe PDFView/Open
chapter 4.pdf1.48 MBAdobe PDFView/Open
chapter 5.pdf963.67 kBAdobe PDFView/Open
chapter 6.pdf375.26 kBAdobe PDFView/Open
executive summary.pdf355.74 kBAdobe PDFView/Open
list of abbreviations.pdf551.57 kBAdobe PDFView/Open
list of figures.pdf382.31 kBAdobe PDFView/Open
list of publications.pdf161.72 kBAdobe PDFView/Open
list of tables.pdf548.93 kBAdobe PDFView/Open
references.pdf417.84 kBAdobe PDFView/Open
table of contents.pdf382.37 kBAdobe PDFView/Open
title.pdf237.92 kBAdobe PDFView/Open
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