Investigations on power minimization in certain cmos digital vlsi circuits

Abstract

Reducing the power dissipation of Integrated Circuits IC through newlinedesign developments is a major challenge in the design of portable systems newlinehigh performance processors and memories The limited battery lifetime newlineimposes very strict demands on the overall power dissipation of a portable newlinesystem Also the increase in leakage currents with continuous trends in Very newlineLarge Scale Integration VLSI technology scaling is a major concern for newlinedeep submicron DSM circuit designers Furthermore chip reliability and newlinelife expectancy of chips decrease with reduced supply voltage and increased newlineleakage Hence low power design of digital integrated circuits has emerged newlineas a very active and rapidly developing field of Complementary Metal Oxide newlineSemiconductor CMOS design The methodologies used to achieve low newlinepower consumption in digital systems span a wide range from deviceprocess newlinelevel to algorithm level newline newline