Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/268459
Title: Design And Analysis of Nanoscale Junctionless Double Gate MOSFET
Researcher: Dhiman, Gaurav
Guide(s): Pourush,Rajeev
Keywords: Electronics and Communication Engineering
Engineering and Technology,Engineering,Instruments and Instrumentation
MOSFET
University: Mody University of Science and Technology
Completed Date: 2018
Abstract: The field effect transistors (FETs) fabricated in integrated circuits are majorly with newlinejunctions. Due to the device scaling down, the fabrication of these junctions has become newlinegradually more difficult. Also, there is a stringent necessity for having high doping newlineconcentration gradient for the smooth functioning of the device. Recently, researchers are newlinefocusing on new devices where devices are junction less and no doping gradient newlinerequirement. One such structure is the junctionless double gate MOSFET (JL-DG newlineMOSFET) which has shown improved performance against short channel effect, namely newlinedrain induced barrier lowering (DIBL), changes in threshold voltage etc. The work newlineconsiders a physical 2-D model of the threshold voltage to study JL-DG MOSFET. The newlinemodel helps to investigate the threshold voltage degradation due to MOSFET parameters newlinenamely, silicon channel layer thickness, silicon dioxide (SiO2) layer thickness, drain bias newlineand effective gate channel length. With the scaling equation in volume conduction mode, a newlinethreshold voltage for nanoscale JL-DG MOSFETs is studied. The model studied can newlinefurther be used for modeling the junction based devices. The junctionless devices have newlineshown to give improved performance than the junction based device in terms of newlineconsiderable reduction in threshold voltage roll-off, DIBL and an increase in technology newlinespace. In the recent past, the channel lengths for conventional single gate MOSFETs have newlinereduced below 45 nm and gate oxide thickness have also reduced below 2 nm. Due to newlinethese factors, there are considerable improvements in performance and packing density. newlineScaling of gate oxide layers led to a reduction in the thickness to around 1 nm which newlineresults in large leakage currents. So replacement of silicon dioxide (SiO2) with a material newlineviii newline newlinehaving a higher dielectric constant (and#954;) or high-and#954; gate oxides such as hafnium oxide newline(HfO2) and hafnium silicate (HfO4Si) is necessary. newline
Pagination: xx,136
URI: http://hdl.handle.net/10603/268459
Appears in Departments:School of Engineering and Technology

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02_certificate.pdf171 kBAdobe PDFView/Open
03_preliminary pages.pdf246.95 kBAdobe PDFView/Open
04_chapter 1.pdf835.06 kBAdobe PDFView/Open
05_chapter 2.pdf379.58 kBAdobe PDFView/Open
06_chapter 3.pdf669.03 kBAdobe PDFView/Open
07_chapter 4.pdf1.01 MBAdobe PDFView/Open
08_chapter 5.pdf438.9 kBAdobe PDFView/Open
09_chapter 6.pdf3.07 MBAdobe PDFView/Open
10_chapter 7.pdf163.87 kBAdobe PDFView/Open
10_list of publications.pdf190.12 kBAdobe PDFView/Open
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