Analysis of low power accuracy substitution circuit in vlsi subsystems

Abstract

In general image processing can get benefit by computerized tomography from hardware acceleration. To design this intensive image processing algorithm, requires the rapid processing of large data. Power minimization has developed into an endlessly more significant concern in the design of very large scale integrated circuits. In modern years, error tolerant design, which is based on the concept of trading off exactness for enhanced power efficiency, has involved major consideration. Applications that are both process demanding and error tolerant are most appropriate to implement error tolerant strategies. This includes digital image processing, digital mining algorithms. Such relaxed circuits can be achieved at some design levels, ranging from software, algorithm and design, down to gate logic levels or transistor levels. This dissertation investigates three research outfits for the design and analysis of low power accuracy trade off circuits at the gate level: 1) Design and implementation of low power accuracy substitution adder and multiplier. 2) Self error detection and correction techniques for implementing low power accuracy substitution circuit under general error specifications. 3) To implement the low power accuracy substitution circuit in image sharpening filter of image processing application. The first thread investigates basic mathematic blocks, such as adders and multipliers, which are at the heart of all information processing and regularly utilize the majority of the power in a circuit. An optimal strategy is developed to reduce power consumption in conventional adders under gate level reduction. This allows a proper manifestation that, in inaccuracy process established in image processing applications, an adder design approach that separates the Most Significant Bits (MSBs) from the Least Significant Bits (LSBs) is most favorable. A best possible uncertain reason is additional planned for the LSBs and which properly use self compensate circuit for the incidence of errors in the MSB section. There is a plentiful originate gap of finest adders defined by discrete gate level logic. newline newline newline