Design and implementation of high speed vedic multiplier

Abstract

Multipliers play a vital role in many signal processing applications. The Digital Signal Processing operations like convolution, Fast Fourier Transform (FFT) are mainly focussed on multiplication for its operations. The operations require multiplication for its functioning. The processor works on digital signal due to its high noise margin. The latest multi-media products, electronic and digital systems operate on high speed with low power. Therefore, it is necessary to design a high speed binary multiplier with compact size for the design of all portable devices. Multiplication is generally calculated by shift-and-add operation. The multiplication operation is carried out in three steps. Initially, the partial products are generated by multiplying the inputs bit-wise. In the next step, the generated partial products get reduced. Finally, the sum of all reduced partial products is carried out using high speed adders. The multiplication algorithms differ in the way by which the partial products are generated and they are summed together. The multiplication process is of two types, namely series multiplication and parallel multiplication. The design of serial multiplication is easy and requires fewer components. The microprocessors and DSP Processors are based on sequential operation. The parallel algorithms are used in high speed processors like Field Programmable Gate Array (FPGA). newline newline newline