High speed hybrid adder architectures for 3x hard multiple generation in radix8 booth encoding

Abstract

High performance processors are essential for multimedia, video recorders, medical imaging and defence applications. With the advent of VLSI, it is advantageous to design an IC that is customized to a particular system or application rather than using standard ICs. Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and area of an Application Specific Integrated Circuit (ASIC). In order to improve the system performance, dedicated multiplier units and memory modules are embedded in high performance processors. newlineThe goal of this research is to design high speed multipliers for signal processing applications. Modified booth algorithm is the ideal choice in most of the high speed multipliers. Therefore the focus of this research narrows down to design of Booth encoder. In most commercial processors, enhancing the speed of the multiplication using the radix-8 booth encoding is the preferred option. In the radix-8 architecture, the 3X (Hard multiple) generation is a major bottleneck. Multiplication is performed by repetitive additions of the multiplicand, and hence adders are the critical components of a data path module. Various adder architectures for 3X(=2X+X) addition have been reviewed. The review maps a set of architectures suitable for 3X addition for various bit width, which reveals that performance characteristics vary over wide range and often in contradiction to each other newline newline newline